1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
In a semiconductor device of the 65 nm node generation and thereafter, decrease in device size and increase in device speed strengthen the following tendencies: (1) a copper (Cu) interconnection is adopted; and (2) an insulating film having a porous structure is used for an interlayer insulating film.
Japanese Laid-Open Patent Application JP-P2005-79116 discloses a method of manufacturing a semiconductor device whose object is to prevent barrier metal or interconnection material such as Cu or the like from diffusing into an interlayer insulating film. The manufacturing method includes: a process of forming a thin film made of insulating material; a process of punching a hole in the thin film; a process of exposing the thin film to an atmosphere of noble gas plasma; and a process of depositing conductive material to fill in the hole. It is described in the patent document that the diffusion of the barrier metal or the interconnection material into the interlayer insulating film can be thereby prevented reliably and easily.
Japanese Laid-Open Patent Application JP-P2002-43315 discloses a technique of forming a layer containing cobalt on a surface of a copper interconnection through an immersion plating method by the use of metal catalyst.
Japanese Laid-Open Patent Application JP-P2000-200832 discloses a technology for increasing adhesiveness of an inorganic barrier film with respect to a copper interconnection or a copper barrier which exists in an interconnecting structure such as a dual damascene structure in a semiconductor device. For that purpose, a reduction plasma treatment process using gas selected from H2, N2, NH3, noble gas, and mixture of these gases is employed.